Finite State Machine Based Reconfigurable Architecture For Image Processor

Adaptively evolvable systems require some reconfigurable capabilities, habituated within the FPGA. FPGA’s can be integrated with either Dynamic Partial Reconfiguration (DPR) or Virtual Reconfiguration Circuits (VRC). Since DPR allows lesser resource utilization on the FPGA available logic, which has a positive repercussion in power consumption compared to VRC’s, we are using FPGA’s with native DPR as our reconfigurable hardware. Evolvable hardware system has been employed to ease automation, in which the reconfiguration is driven by an evolutionary algorithm. Choosing evolutionary algorithm for DPR over the optimization algorithms is because these algorithms are incremental, and hence the processing circuit will be affected only by small changes reducing the reconfiguration times. One of the problems of the evolvable systems is that, they have to be trained to the conditions in which the system will operate. The generation of this training data is done offline, reducing the system’s autonomy. We have proposed the enhancement of this evolvable system by injecting the concept of Finite State Machine which reduces its dependence. Considering that our system concentrates on adaptive image processing, we have utilized the Self Tuning Architecture (STA) based on FSM and combined them with the evolutionary algorithm, to implement the image processor. KEYWORDS—Evolvable Hardware, FSM, Evolutionary Algorithm, Dynamic Partial Reconfiguration.